An Input/Output (IO) interface circuit 104 may interface an IO pad 102 of an Integrated Circuit (IC) with an IO receiver 106, as shown in FIG. 1. The IO pad may allow for the IC to be connected to external devices. The IC system 100 of FIG. 1 may require different voltage levels for the IO pad 102 and the IO receiver 106. For example, the voltage at the IO pad 102 may be high (e.g., 3.465, 5.5 V, or, 3.3 V+5% tolerance, 5V+10% tolerance) and the operating voltage of the IO receiver may be low (e.g., 2.5 V). The supply voltage may also be at a different voltage level.
The constituent active elements (e.g., Metal-Oxide-Semiconductor (MOS) transistors) of the IO interface circuit 104 and the IO receiver 106 may also have an upper tolerable limit of the operating voltage thereof (e.g., 1.98 V, or, 1.8 V+10% tolerance). When a voltage higher than the operating voltage of the receiver (e.g., 2.5 V) is input to the receiver, constituent active elements of the IO receiver 106 may be stressed, which may affect the reliability of the IO receiver 106. Similarly, the constituent active elements of the IO interface circuit 104 may also be stressed.
Considering a MOS transistor as the active element, when the voltage across the drain (D) terminal and the gate (G) terminal of the MOS transistor exceeds an upper limit, the gate (G) oxide of the MOS transistor under stress may break down.